A pipelined ADC using a Background Calibration with a High-pass Mismatch Shaper and Delta-Sigma Modulation

The mismatch results from the manufacturing error of the capacitor that composes internal DAC deteriorated SNR and THD. This paper presents a new back-ground digital calibration method for precise and high-speed mismatch detection of a pipelined ADC. In the conventional method, the mismatch of the capacitor cannot be detected accurately. The proposed method is a combination of high-pass delta-sigma modulation and Noise-Shaping Dynamic Element Matching (NSDEM). The simulation results show that the proposed method can improve the error detection accuracy and speed, and realize a 14-bit conversion accuracy with 1% capacitor mismatches. The signal-to-noise distortion ratio and total harmonic distortion are greatly improved by 24.0dB and 26.0dB.